In a memory array such as a register file array, the minimum operating voltage (VCCmin) of the memory array is typically limited by the write and/or read operation of the memory array. This is due to the contention between the negative-channel metal-oxide-semiconductor field effect transistor (MOSFET) (NMOS) devices and the positive-channel MOSFET (PMOS) devices in the memory array. The contention poses a problem for a system that employs the memory array, especially when the VCCmin of the memory array limits the VCCmin of the entire system.
FIG. 1 illustrates a prior art shared PMOS scheme 100 in a register file bit cell 110. The register file bit cell 110 illustrates one of the bit cells in a register file. The register file bit cell 110 has cross-coupled transistors 111, 112, 113 and 114. The transistors 115 and 116 allow access to a complementary bit (bitx) node 122 and a bit node 120 respectively. The bit node 120 and the bitx node 122 stores the bit value and complementary bit value of the register file bit cell 110 respectively. When the write word line 140 enables the transistors 115 and 116, the write input 130 allows the data to be written to the register file bit cell 110 via the write bit line 150 and the complementary bit line 155. The value of the bit node 120 can be read using the transistors 117 and 118 via the read bit line 170 when the read word line 160 enables the transistor 118.
The PMOS transistor 119 is connected to the PMOS transistors 111 and 112 and is also connected or shared with the other PMOS transistors in the other register file bit cells. The PMOS transistor 119 weakens the pull-up strength of the PMOS transistors 111 and 112 and improves the write jamming ratio, i.e., the ratio of the strength of the NMOS transistor 115 to the effective strength of the PMOS transistors 111 and 119.
However, as the size of transistors becomes smaller and smaller, the prior art shared PMOS scheme 100 is unable to keep up with the reduction in the VCCmin of the register files. The size of the NMOS transistors 115 and 116 can be increased to improve write jamming ratio but the area of the bit cell would have to be increased.